1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor device and a method of manufacturing the same, capable of simplifying manufacturing processes and highly integrating devices while reducing ON resistance.
2. Description of the Related art
FIG. 1 is a cross-sectional view of the structure of a conventional semiconductor device and FIG. 2 is a cross-sectional view of the structure of another conventional semiconductor device.
The super-junction structure of a semiconductor device is obtained by substituting a drift region of a MOSFET device having a normal electric power with a vertical PN junction structure, and this structure uniformly distributes an electric field when the device is in an OFF state, thereby improving the breakdown voltage.
The super-junction structure of a conventional semiconductor device is illustrated in FIG. 1. As shown in FIG. 1, an N-type epitaxial layer 11 is grown on an N-type substrate 10 and a gate insulating layer 12 and a gate electrode 13 are integrated on a portion of the N-type epitaxial layer 11. On the substrate 10 isolated from the gate electrode 13, a source electrode 14 is formed. In addition, a first P-type doped region 15 extends from a bottom portion of the gate electrode 13 to a predetermined depth of the substrate 10. In addition, a second N-type doped region 16 is formed at both bottom portions of the gate electrode 13 and the source electrode 14 and at the surface portion of the first doping region 15 formed between the gate electrode 13 and the source electrode 14.
In this manner, a conventional vertical PN junction is achieved.
In addition, in a semiconductor device manufactured according to another conventional method as illustrated in FIG. 2, a trench is formed at both side portions of an active region, and N-type and P-type ions are implanted onto both side wall portions of the trench, thereby obtaining the vertical PN junction structure.
That is, a first N-type doping region 21 is formed in a substrate 20 and a gate insulation layer 24 and a gate electrode 25 are integrated on the substrate 20. And, a source electrode 26 is formed at one portion of the substrate 20 insulated from the gate electrode 25. First and second trenches 22a and 22b are formed under both side portions of the gate electrode 25 and the source electrode 26, and a trench isolation layer 23 is formed at each trench.
At one side region of each trench insulation layer 23, a second P-type ion implanted doping region 27 is formed. In addition, a third N-type doping region 28 is formed on the surface portion of the second P-type doped region 27 and between the source electrode 26 and the gate electrode 25.
As described above, a trench is formed at both side regions of the active region and a vertical PN junction region is formed between the trenches in FIG. 2.
However, in order to obtain the super-junction structure having a sufficient depth in the above-described conventional semiconductor device, the processes of growing an epitaxial layer and implanting ions must be repeated several times.
Moreover, since the semiconductor device has a horizontal gate structure, one channel is present at one active region, so that it is limited to increase the device density.
The present invention has been made to solve the above problems, and an object of the present invention to provide a semiconductor device having a vertical trench gate structure to improve the integration degree of the device and a method of manufacturing the same.